The increasing integration of semiconductor components, the increasing number of necessary electrical connections between semiconductor chips and carrier elements and, in particular, the requisite miniaturization with the aim of the flattest possible subassemblies, have led to the practice of making direct contact between semiconductor chips and carrier elements, e.g., flip-chip bonding. This practice has led to a considerable simplification of semiconductoir mounting technology, since metallic intermediate carriers and the production of wire links are no longer required in order to make electrical contact.
However, in order to make possible the direct contact between semiconductor chips and carrier elements such as printed circuit boards (“PCBs”), it is necessary to produce 3D structures, known as bumps or soldering mounds, on the semiconductor chip, which at their respective highest point have a gold-plated contact surface and are connected via a conductor track to a bonding pad of the wafer. These gold-plated contact surfaces can then be provided with a micro ball or the like of a solder material and connected electrically and mechanically to a corresponding soldering contact on the PCB.
In order to achieve a certain equalization of mechanical loadings on the completed subassemblies, for example caused by different thermal coefficients of expansion of the individual components or caused during their handling, the basic structure of the bumps is produced from a compliant material, e.g., silicone, so that a three-dimensional, mechanically flexible structure is produced.
The conductor tracks used for the electrical connection between the bonding pads and the bumps consist, for example, of a seed layer, on which a Cu conductor track and, above the Cu conductor track, a Ni layer are grown, the latter being used to protect the Cu layer against corrosion. A dielectric is used underneath the seed layer and the bumps to ensure that there is an electrical connection only between the gold-plated contact surface on the bump and the associated bonding pad.
In order to achieve solderability, the nickel layer must be coated with gold at the appropriate points, i.e., the tips of the three-dimensional (“3D”) structures.
In the process, it is absolutely necessary to ensure that the gold coating is applied only to the tips of the 3D structures and that the redistribution layer, which leads down from the 3D structures, is absolutely free of gold. This creates a solder stop when the semiconductor chip is soldered onto a carrier element. Without this solder stop, the solder material would flow in an uncontrolled manner over the redistribution layer and have a detrimental effect on mechanical and electrical properties which could negatively impact the reliability of the finished electronic subassembly.
In the method commonly used in present manufcaturing processes, the necessary structuring of the gold layer is implemented by means of a generally known lithographic process. In this method, immediately after the seed layer and the Cu/Ni layer of the redistribution layer are applied, the gold is deposited on the entire redistribution layer. The gold layer is then covered by lithography in such a way that selective etching or stripping of the undesired gold layer can be performed. Upon completion of this method, a gold layer remains only immediately on the tip of the 3D structure.
In further detail, this currently-used method is performed using the following steps. First, the deposition of the seed layer is performed. Next, an EPR1 (epoxy photoresist 1) coating and structuring is applied during the first lithography step. Next, the reroute plating, production of the Cu/Ni layer on the seed layer is completed. The reroute trace is then coated with Au. Next, EPR2 (epoxy photoresist 2) coating and structuring is performed as a second lithography step. Finally, the Au layer is selectively etched using wet etching or removal/stripping techniques.
The result of this process is a 3D structure with a gold coating on its tip. However, the side flanks of the structure remain unprotected. While this may ensure that, during the subsequent connection of the wafer to a PCB, no solder material can flow away laterally over the flanks of the 3D structure (which could lead to functional disruption), the Ni layer is likewise exposed during the Au etching/stripping is accordingly completely unprotected against corrosion. This is a significant disadvantage of this known method.
In another method which is commonly used in practice, the 3D structures are initially connected to the associated bonding pad as already described with conductor tracks of Au-coated Cu/Ni layers and are subsequently embedded in a potting compound in such a way that only the tips of the 3D structures remain free. However, this method is difficult to perform properly and can be inefficient.